Mohammad Azadi - Master

This paper presents a design of a switched-capacitor discrete time 1st order Delta-Sigma modulator by using latch comparator. Procedures for obtaining the design specifications needed for its modeling in HSPISE are presented. Simulation results showed that with 0.18um CMOS technology, 12 MHz sampling frequency and oversampling rate of 64, the modulator achieved 53.8 dB Signal to Noise Ratio (SNR) and the power consumption was 1.58 mW under ±1.8V supply voltage .

sigma delta ; modulator; converter; analog to digita