Jitter Noise Alleviation Through Parallel Sampling and Averaging

Sampling jitter severely impacts the performance of Analog to Digital Convertors (ADC). In this paper, we propose a simple, yet effective parallel sampling architecture, in which average output of several Sample & Hold circuits is calculated in analog domain prior to quantization. We show analytically our architecture reduces the variance of the timing jitter and consequently mitigates the jitter associated noise. We also, demonstrate through simulations that the proposed architecture can increase Signal to Noise Ratio (SNR) of the sampled signal around 6dBs for every doubling in number of sampling channels.

کلیدواژه ها:

Sampling Uncertainty ، Jitter Error ، ، Analog to Digital Convertorsion ، Jitter Correction