A High Speed Low Power Signed Digit Adder
محل انتشار: شانزدهمین کنفرانس مهندسی برق ایران
سال انتشار: 1387
نوع سند: مقاله کنفرانسی
زبان: انگلیسی
مشاهده: 2,896
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شناسه ملی سند علمی:
ICEE16_006
تاریخ نمایه سازی: 6 اسفند 1386
چکیده مقاله:
Signed digit (SD) number systems provide the possibility of constant-time addition, where interdigit carry propagation is eliminated. Such carry-free addition is primarily a three-step process. The special case of maximally redundant SD number systems leads to more efficient carry-free addition. This has been previously achieved based on speculation of transfer values and use of three parallel adders. We propose an alternative nonspeculative addition scheme that computes the transfer values through a fast combinational logic. The proposed carry-free addition scheme is shown to improve performance in terms of speed, power and area. The simulation and synthesis of three previous works and this work, based on 0.13 μm CMOS technology, confirms the latter claim.
کلیدواژه ها:
نویسندگان
Ghassem Jaberipur
Department of Electrical and Computer Engineering, Shahid Beheshti University and
Saeid Gorgin
School of Computer Science, the institute of theoretical physics and mathematics(IPM), Tehran, Iran