A SAR ADC with an Efficient Threshold Voltage Generation

A new architecture is proposed in which with respect to the conventional successive approximation register (SAR) analog-to-digital converter (ADC), the switching power andcapacitor area are significantly reduced without an appreciable increase in digital complexity. In the proposed scheme, thethreshold voltage for each comparison is divided into two parts where producing these two parts consumes appreciably less switching energy and requires less total capacitance than the conventional one. With respect to the conventional scheme, the switching power and total capacitance of the proposed SARADC for 10 bit resolution is reduced by more than 87% and 40%, respectively.