Low Power Design of Successive Approximation Registers

This paper presents low power design methods for successive approximation registers (SARs) that may serve as the digital part of a successive approximation analog to digital converter (SA-ADC). The SAR is designed in 130nm technology in the sub-threshold region to meet the goal of reduced power consumption.

کلیدواژه ها:

Analog to Digital Converter ، Clock ، Dynamic Register ، Static Register