Leakage Power Reduction in Nanoscale FPGA Structures

A key challenge in the IC VDSM/Nano scaling era is providing high-performance solutions while minimizing power and cost. Programmable logic devices such as field-programmable gate arrays (FPGAs) address this challenge by introducing a cost-efficient solution from low to mid volume applications due to low non-recurring engineering costs. Additionally, with in-field programmability, FPGAs provide a platform solution with faster time to market and longer product lifetime. Despite its many advantages, FPGAs are not widely found in today’s mobile applications.Despite FPGAs’ computational energy efficiency advantage over digital signal processors (DSPs), DSPs are widely used in battery-operated applications primarily due to their extensive power management capabilities that enable very low-power consumption during standby. In contrast, existing FPGAs, designed for high throughput, high-duty-cycle applications, have little or no power management features. Thus Low-power FPGA design has recently become an area of research interest. In the area of hardware design, low-power techniques such as low-swing interconnect, heterogeneous interconnect, multi-Vt, multi- VDD, and fine-grain power gating have been proposed to improve FPGAs power consumption.By using programmable VDD, logic blocks connect to either low VDD or high VDD depending on their speed. The CLBs on critical path must connect to VDDH in order to keep their delay in the desire range but other CLBs can connect to VDDL to reduce power consumption. Power gating is another method to reduce power in standby mode. In this method a power transistor inserted between logic block and VDD. There are power and delay overheads associated with the insertion of power transistors. This is because the power transistors stay either ON or OFF after configuration and there is no charging or discharging at their source/drain capacitors