This paper addresses the design of an application-specific processor for medium-speed packet processing upp(icanbns. Wi~hinth is domain, increasing performance demands and the ongoing development of nenvark protocols both call for flexible and per-once-optimized processors. Our approach begins wirh a quantirotive study of a typical network application based on the implementation ond profiling of layer-2 switching on two diflrent generol purpose processors (GPP). n i s study b pe.$ormed to befler understand the main challenges and tradeofs iin using such processors for network applications, and also, helps to identi& the architectural guidelines for sziccessfil development of an application specific instruction processor (ASIP) for packet processing applications. To achieve this goal, we have performed several switching experiments using PowerPC and LEON2 processors and propose an optimized layer-2 packet processor in terms of architecture and instruction set.

Layer-2 switching, packet processing, network processors, special purpose processor, ASIP