Mirzaaghatabar - Sharif University of Technology, Tehran, Iran
Hessabi - Sharif University of Technology, Tehran, Iran
Pedram - Amirkabir University of Technology, Tehran, Iran

Lack of global clock for synchronization in asynchronous circuits decreases the controllability of these circuits and thus makes asynchronous circuits hard to test. Delay Insensitive (DI) circuits exclusively use C-elements and inverters, provided that only single output gates are used. In this paper we present a new method to conceptually change this class of asynchronous circuits. The main idea is to change C-elements into other elements which can be modeled by synchronous tools. Then we use HOPE, a synchronous sequential circuits fault simulator, and apply it to DI class of asynchronous circuits. The stuck-at model is used for fault simulation. Our observations show that we can achieve considerable fault coverage, mainly 92.5%, in DI circuits by this method. To the best of our knowledge, this is the first effort in using synchronous tool to achieve fault simulation for asynchronous circuit class.

Fault Simulation, Delay Insensitive circuits, C-elements