Ehsan Yaqubi - Department of Electrical and Computer Engineering Birjand University Birjand, Iran
Seyed Hamid Zahiri - Department of Electrical and Computer Engineering Birjand University Birjand, Iran

In this paper, a modified doubled tail comparator is presented to achieve higher speed. In order to decrease the total delay time, the capacitance load is reduced using an alternative latch. Three topologies of common double tail comparator are studied and re-simulated in the same condition. Simulation results in Hspice 180nm TSMC at VDD=0.8v show 84fF load capacitance which was 137fF before modification. Also average energy consumed per switching event is reduced to 26.88fj from 43.84fj.

Doubled Tail Comparator; High speed; Low power Latch comparator