A Transistor-Level Placement Tool for Asynchronous Circuits
محل انتشار: نهمین کنفرانس سالانه انجمن کامپیوتر ایران
سال انتشار: 1382
نوع سند: مقاله کنفرانسی
زبان: انگلیسی
مشاهده: 2,376
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شناسه ملی سند علمی:
ACCSI09_095
تاریخ نمایه سازی: 4 بهمن 1386
چکیده مقاله:
Although asynchronous circuits are accepted as low-power, low-EMI and high-performance circuits, the roadblock to wide acceptance of asynchronous design methodology is poor CAD support, especially physical design tool. There are few academic design tools for
asynchronous circuit design and synthesis, but there is neither a published tool nor a published document on physical design of these circuits. Since there are noncomplementary CMOS circuits in the netlist synthesized using Caltech synthesis method, the commercial cell-based
placement tools can’t be used. In this paper we have presented a design flow for placement of asynchronous circuits at transistor-level considering their timing constraints.
کلیدواژه ها:
نویسندگان
Saleh
۱Department of Computer Eng. and IT, Amirkabir University of Technology، Iran
Pedram
Department of Computer Eng. and IT, Amirkabir University of Technology، Iran
Zamani
Department of Computer Eng. and IT, Amirkabir University of Technology، Iran
Naderi
Department of Computer Eng. and IT, Amirkabir University of Technology، Iran