Novel Designs of Nanometric Parity Preserving Reversible Circuits

Power consumption is one of the important issues in VLSI design. Reversible logic produces zero power; therefore, nowadays researchers attend to it in order to optimize power. In the digital systems, one of the methods of achieving to fault tolerance is parity preserving. This paper proposes a new parity preserving reversible gate, PPRG. The most significant aspect of the PPRG gate is that it can be used to produce parity preserving reversible full adder circuit. This circuit is more efficient than the existing designs in term of quantum cost and it is optimized in terms of number of constant inputs and garbage outputs. A novel parity preserving reversible 4:2 compressor is also proposed using the PPRG gate. It is the first attempt to design parity preserving reversible 4:2 compressor. Thus, this paper is the good initiator for building more complex parity preserving reversible circuits.

کلیدواژه ها:

Compressor ، Nanometric ، Parity Preservation ، Reversible Logic