A Novel 54x54-bit Scalable Multiplier Architecture

Implementation of parallel multipliers with operands meeting IEEE 754 standard could involve a 27:2 compression of partial products. In this paper we offer a new design which is suitable for low power and high speed processing environment, more than 41% of carry-in/out wires are eliminated in our design. By using this new design, when cascading a chain of this kind of compressor we achieve evens more performance and less chip area. While the whole design is coded in VHDL language and the implementation gives comparable results to full custom designs [3, 4]. Realistic simulations using extracted timing parameters from the layout show that the propagation time of a critical path is almost 26% for sum and 29% for carry faster than the conventional 27:2 compressor.

کلیدواژه ها:

VLSI Design ، Compressor ، Adder ، Booth Encoder ، Wallace tree ، Multiplier