Programmable Routing Tables for Degradable Mesh-Based Networks on Chips

سال انتشار: 1386
نوع سند: مقاله کنفرانسی
زبان: انگلیسی
مشاهده: 1,781

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شناسه ملی سند علمی:

ICEE15_251

تاریخ نمایه سازی: 17 بهمن 1385

چکیده مقاله:

The Decreasing manufacturing yield of integrated circuits, as a result of rising complexity and decreased feature size, and the emergence of NoCbased design techniques, has necessitated the search for network reconjguration techniques for reusing NoCs with faulty communication hardware. In this paper, we propose a method to cope with the problem of faulty ports in NoCs with mesh topology. The method is based on the use of reconJigurable routing tables in network switches. We investigate this technique for a conventional routing mechanism and our optimized routing approach. The conventional mechanism uses one entry in its routing table for eveiy destination address while our proposed routing mechanism uses ajxed number of entries per table and routes based on the address value comparison of the current switch and the destination switch. Experimental results show that a network reconzred for fault masking by programming its routing tables has acceptable but degraded performance parameters as compared to the original, non-faulty network.

نویسندگان

Shahabi

CAD Laboratory, School of Electrical and Computer Engineering, University of Tehran, Tehran, IRAN

Honarmand

CAD Laboratory, School of Electrical and Computer Engineering, University of Tehran, Tehran, IRAN

Navabi

CAD Laboratory, School of Electrical and Computer Engineering, University of Tehran, Tehran, IRAN

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  • semiconductor Industy Association, International Techrology Roadmap for Semicon ductors, World ...
  • R. Saleh et al., _ Sy stem-on-Chip: Reuse ad Integration, ...
  • L. Benini and G. De Micheli, "Networks on chips: _ ...
  • P.P. Pamde et al., "Design, Synthesis, ad Test of Network ...
  • J. Duato, S. Yalamanchili, ad L. _ _ tercornection Networks-An ...
  • s. Kumar et al., "A Network _ Chip Architecture and ...
  • _ W.J. Dally and B. Towles, "Route Packets, Not Wires: ...
  • F. Karim, A. Nguyen, ad S. Dey, "An Intemconuect Architectue ...
  • P. Guerrier ad A. Greiner, "A generic architecture for on-chip ...
  • P.P. Pande, C. Grecu, A. Ivaov, and R. Saleh, "Design ...
  • N. Honarmand, A.Shahabi, H. Sohofi, M. Abbaspour, aod Z. Navabi, ...
  • M. Yang, T. Li, Y. Jiang, and Y. Yang, [_ ...
  • R. Marculescu, "Networks -on-Chip _ The Quest for On- Chip ...
  • C. Grecu et al., "On-line Fault Detection ad Location for ...
  • نمایش کامل مراجع