A Low-Power Low-Area Architecture Design for Distributed Arithmetic (DA) Unit

In this paper an improved DA architecture is proposed. In the proposed DA, the high power consumption adder units are relocated in the system to lower the switchingactivity and total power. The proposed DA exploits the circuit activity and the adder units are only used just in minimum states. The designed DA is a run-time reconfigurable. Thedesign is verified, and simulation results via 2-phase power calculations based on forward synthesis invariant approachand back ward synthesis oriented activity approach is used to calculate the power and area of the proposed DA and allknown counterparts. In the experimental results on 180n CMOS ASIC synthesis the maximum clock of 180 MHz is achieved. In the 5-tape FIR filter implementation of ourproposed DA with clock gating enabled and best known LUT Less2, the dynamic power and area improvements are 39.76% and 16.35% respectively

کلیدواژه ها:

Multiply-Accumulator-Circuit (MAC) ، Distributed Arithmetic (DA) ، Finite-Impulse-Response (FIR) Filter