A Parallel High Speed General Architecture for Digital Fuzzy Logic Controllers

This paper presents design and implementation of a general parallel high speed architecture for digital Fuzzy Logic Controller (FLC). The proposed design is in structural level inwhich adder, multiplier, and divider used in FLC have Fine- Grain multiplexer based pipelined array structure. Simulationswere carried out by using DSP builder in MATLAB/Simulink and the architecture has been successfully synthesized andimplemented using Quartus II 9.1and StratixII FPGA for a 2- input 1-output FLC, with 8 rules and maximum clock rate of 301.84 MHz

کلیدواژه ها:

Digital Fuzzy Logic Controller ، Fine-Grain Pipelining ، FPGA