Multi-Objective Optimization of a Low-Offset and Low-Power Latched Comparator

This paper presents an optimal design of a low-offset and low-power latch comparator only by adjusting transistors widths. To reach a reliable design, the Multi-Objective Inclined Planes Optimization (a heuristic algorithm) and Hspice are used mutually. A Pareto front is obtained from this link, which suggests several designs for comparator. As a result, the obtained Pareto front shows a tradeoff between power and offset. From the Pareto front, a final design is selected and re-simulated in Hspice TSMC 180nm at VDD=0.6v. To measure the random offset due to the mismatch in Vth, W and L of transistors, a 100-run of Monte-Carlo simulation is accomplished. For the final design, 1-sigma offset is 0.231mv and power consumption is 46nw.

کلیدواژه ها:

Multi-Objective ، Inclined Planes Optimization ، low-offset ، low-power ، Comparator