Double N+ Silicon Windows In Active Region And Buried Oxide Of LDMOS To Achieve NHigh Breakdown Voltage And Low Lattice Temperature

A new device structure for high breakdown voltage and low maximum lattice temperature of LDMOS device is proposed in this paper which is called DNW-LDMOS. The main idea in the proposed structure is locating double N+ silicon windows in active region and buried oxide to have high breakdown voltage. In the proposed transistor, using N+ window in the BOX reduces lattice temperature because of high thermal conductivity of silicon that raises the reliability of the proposed structure. the simulation with two-dimensional ATLAS simulator shows that locating N+ silicon window which has higher doping density than drift region reduces the on-resistance significantly. So, this behavior causes the switching usage of the DNW-LDMOS. In the conventional structure, self heating effect causes reduced drain current in higher drain voltage, in which the proposed DNW-LDMOS has an acceptable drain current in all ranges.

کلیدواژه ها:

LDMOS ، breakdown voltage ، lattice temperature ، reliability