Efficient Area and Speed Optimized Multiplication Technique Using Vedic and Tree Addition Structure

Now days we are living in digital world, where all the operations get performed more reliably and with highest accuracy by digital signal processor. The multiplier is thekey element of all these processor like Microprocessor, Microcontroller, DSP processor etc. After through study and deep analysis work we have seen that the existing Vedic multiplication hardware has some limitation in terms of area. To overcome these limitations a novel approachhas been proposed to design the Vedic multiplier with unique addition structure, which is used to add partially generated products. To meet our major concern ‘Speed’ weneed particular high speed multiplier, the speed of multiplier greatly depends upon the type of multiplicationtechnique used in it. We have come up with the idea tomerge two different multiplication techniques Vedic and Tree addition structure and these gives us a fast and area efficient multiplication approach.