High-performance and Low-power Clock Branch Sharing Pseudo-NMOS Level Converting Flip-flop
محل انتشار: ماهنامه بین المللی مهندسی، دوره: 26، شماره: 3
سال انتشار: 1391
نوع سند: مقاله ژورنالی
زبان: انگلیسی
مشاهده: 826
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شناسه ملی سند علمی:
JR_IJE-26-3_004
تاریخ نمایه سازی: 17 خرداد 1393
چکیده مقاله:
Multi-supply voltage design using Cluster Voltage Scaling (CVS) is an effective way to reduce power consumption without performance degradation. One of the major issues in this method is performanceand power overhead due to insertion of Level Converting Flip-Flops (LCFF) at the interface from lowsupplyto high-supply clusters to simultaneously perform latching and level conversion. In this paper, an improved version of clocked pseudo-NMOS LCFF called Clock Branch Sharing pseudo-NMOS LCFF has been proposed, which combines the Conditional Discharge technique, pseudo-NMOStechnique and Clock Branch Sharing technique. Based on Simulation results, the proposed flip-flop exhibits up to 32.5% delay reduction and saves power up to 8.1% as compared to clocked pseudo- NMOS LCFF.
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نویسندگان
k juneja
Department of Electronics and Communication, National Institute of Technology, Kurukshetra, India
n.p singh
Department of Electronics and Communication, National Institute of Technology, Kurukshetra, India
y.k sharma
Department of Electronics and Communication, National Institute of Technology, Kurukshetra, India