A Novel Design of Reversible Multiplier Circuit
محل انتشار: ماهنامه بین المللی مهندسی، دوره: 26، شماره: 6
سال انتشار: 1392
نوع سند: مقاله ژورنالی
زبان: انگلیسی
مشاهده: 916
فایل این مقاله در 10 صفحه با فرمت PDF قابل دریافت می باشد
- صدور گواهی نمایه سازی
- من نویسنده این مقاله هستم
استخراج به نرم افزارهای پژوهشی:
شناسه ملی سند علمی:
JR_IJE-26-6_006
تاریخ نمایه سازی: 17 خرداد 1393
چکیده مقاله:
Adders and multipliers are two main parts of arithmetic units of computer hardware and play important role in reversible computations. This paper introduces a novel reversible 4×4 multiplier circuit that isbased on an advanced Partial Product Generation Circuits (PPGC) with Peres gates only withoutduplicating gates. Again, an optimized Peres full adder reversible gate is used in Reversible Parallel Adder (RPA) part with accompaniment with the carry save adder technique. Comparison of the proposed design with previous ones shows that the proposed reversible multiplier improves thequantum parameters. The proposed design shows lower quantum cost and depth with the help of a novel design in PPGC. The circuit cost of the proposed design is a little higher than the best compared design, but the proposed design shows the lowest total cost which is defined as sum of quantum cost and circuit cost. Moreover, the number of gates, garbage input and output has no change regarding tothe best compared design. The proposed multiplier can be generalized as an n×n bit multiplication
کلیدواژه ها:
نویسندگان
p moallem
Department of Electrical Engineering, University of Isfahan, Isfahan, Iran
m ehsanpour
Department of Computer, Falavarjan Branch, Islamic Azad University, Falavarjan, Isfahan, Iran