Design and Implementation of Digital Demodulator for Frequency Modulated CWRadar

Radar Signal Processing has been an interesting area of research for realization of programmabledigital signal processor using VLSI design techniques. Digital Signal Processing (DSP) algorithmshave been an integral design methodology for implementation of high speed application specific realtimesystems especially for high resolution radar. In recent times, CORDIC algorithm is turned out tobe a huge researched outcome for its easy realizability in on-chip design in the field of vector rotatedDSP applications. In this paper, we propose a pipelined CORDIC architecture for digital demodulationin high performance, low power frequency modulated CW Radar. A complex Digital Phase LockedLoop (DPLL) has been used for digital demodulation with pipelined CORDIC module as its coreprocessing element. The FPGA implementation of CORDIC based design has been chosen because ofits inherent high throughput of system due to its pipelined architecture where latency is reduced in eachof the pipelined stage. Substantial amount of resource utilization has been reduced in proposed design.For better loop performance of first order complex DPLL during demodulation, the convergence of theCORDIC architecture is also optimized. Multiplierless BOXCAR filter has been incorporated at thefinal stage of the design for better information recovery from narrow samples with little energy signaland easy realization. Hardware synthesized result using Cadence design tools are presented.