BIST-based Testing and Diagnosis of LUTs in SRAM-based FPGAs
محل انتشار: مجله ایتالیایی علوم و مهندسی، دوره: 1، شماره: 4
سال انتشار: 1396
نوع سند: مقاله ژورنالی
زبان: انگلیسی
مشاهده: 454
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شناسه ملی سند علمی:
JR_IJSE-1-4_006
تاریخ نمایه سازی: 21 فروردین 1397
چکیده مقاله:
FPGA chips have wide applications in nowadays digital systems. Because of fault prone nature of FPGA chips, testing of them is one of the major challenges for designers. Among various test methods, the Built-in Self-Test (BIST) based ones have shown good performance. In this paper, we presented a BIST-based approach to test LUTs as most vulnerable part of FPGA chip. The BIST-based approach is off-line and has been accomplished within two FPGA configurations. Each configurable logic block (CLB) can be tested independently and there is no handshaking among various CLBs BIST cores. The proposed BIST architecture has been simulated in HSPICE based on 45-nm CMOS technology. Simulation results shown 100% coverage for single stuck at faults along with 19% area overhead due to additional BIST hardware and 25% increase in leakage power
کلیدواژه ها:
نویسندگان
aHadi Jahanirad
Department of Electrical Engineering, University of Kurdistan, Sanandaj, Kurdistan, Iran
Hanieh Karam
Department of Electrical Engineering, University of Kurdistan, Sanandaj, Kurdistan, Iran