Improvement of Tunnel Field Effect Transistor Performance Using Auxiliary Gate and Retrograde Doping in the Channel

سال انتشار: 1398
نوع سند: مقاله ژورنالی
زبان: انگلیسی
مشاهده: 382

فایل این مقاله در 8 صفحه با فرمت PDF قابل دریافت می باشد

استخراج به نرم افزارهای پژوهشی:

لینک ثابت به این مقاله:

شناسه ملی سند علمی:

JR_JECEI-7-1_004

تاریخ نمایه سازی: 13 آذر 1398

چکیده مقاله:

In this work, a dual workfunction gate-source pocket-retrograde doping-tunnel field effect transistor (DWG SP RD-TFET) is proposed and investigated. DWG SP RD-TFET is a Silicon-channel TFET with two isolated metal gates (main gate and auxiliary gate) and a source pocket in the channel close to the source-channel junction to increase the carrier tunneling rate. For further enhancement in the tunneling rate, source doping near the source-channel junction, i.e., underneath the auxiliary gate is heavily doped to create more band bending in energy band diagram. Retrograde doping in the channel along with auxiliary gate over the source region also improve device subthreshold swing and leakage current. Based on our simulation results, excellent electrical characteristics with ION/IOFF ratio > 109, point subthreshold swing (SS) of 6 mV/dec and high gm/ID ratio at room temperature shows that this tunneling FET can be a promising device for low power applications.

کلیدواژه ها:

Tunnel Field Effect Transistor (TFET) ، subthreshold swing (SS) ، source pocket ، isolated gates ، retrograde doping

نویسندگان

Mohammad Karbalaei

Institute of nanoscience and nanotechnology, University of Kashan, Kashan, Iran.

Daryoosh Dideban

Department of Electrical and Computer Engineering

Negin Moezi

Department of Electronics, Technical and Vocational University, Kashan

مراجع و منابع این مقاله:

لیست زیر مراجع و منابع استفاده شده در این مقاله را نمایش می دهد. این مراجع به صورت کاملا ماشینی و بر اساس هوش مصنوعی استخراج شده اند و لذا ممکن است دارای اشکالاتی باشند که به مرور زمان دقت استخراج این محتوا افزایش می یابد. مراجعی که مقالات مربوط به آنها در سیویلیکا نمایه شده و پیدا شده اند، به خود مقاله لینک شده اند :
  • N. S. Shahraki and S. H. Zahiri, Low-Area/Low-Power CMOS Op-Amps ...
  • M. Shaveisi and A. Rezaei, Performance analysis of reversible sequential ...
  • W. Y. Choi and H. K. Lee, Demonstration of hetero-gate-dielectric ...
  • P. Jain, V. Prabhat, and B. Ghosh, Dual metal-double gate ...
  • Y. Taur and E. J. Nowak, CMOS devices below 0.1 ...
  • R. Jhaveri, V. Nagavarapu, and J. C. Woo, Effect of ...
  • C.-M. Kyung, Nano Devices and Circuit Techniques for Low-Energy Applications ...
  • J. K. Mamidala, R. Vishnoi, and P. Pandey, Tunnel Field-Effect ...
  • K. Gopalakrishnan, P. B. Griffin, and J. D. Plummer, I-MOS: ...
  • H. Kam, D. T. Lee, R. T. Howe, and T.-J. ...
  • G. Zhou, Y. Lu, R. Li, Q. Zhang, W. S. ...
  • D. S. Yadav, D. Sharma, B. R. Raad, and V. ...
  • W. Y. Choi and W. Lee, Hetero-gate-dielectric tunneling field-effect transistors, ...
  • M. Shirazi and A. Hassanzadeh, Design of a low voltage ...
  • A. Es-Sakhi and M. Chowdhury, Analysis of device capacitance and ...
  • N. B. Bousari, M. K. Anvarifard, and S. Haji-Nasiri, Improving ...
  • Q. Zhang, W. Zhao, and A. Seabaugh, Low-subthreshold-swing tunnel transistors ...
  • W. Y. Choi, B.-G. Park, J. D. Lee, and T.-J. ...
  • F. Balestra, Tunnel FETs for ultra low power nanoscale devices, ...
  • J. Cao, J. Park, F. Triozon, M. G. Pala, and ...
  • U. E. Avci, R. Rios, K. Kuhn, and I. A. ...
  • Y. Lv, W. Qin, C. Wang, L. Liao, and X. ...
  • R. N. Sajjad, U. Radhakrishna, and D. A. Antoniadis, A ...
  • A. Shaker, M. El Sabbagh, and M. M. El-Banna, Influence ...
  • S. Garg and S. Saurabh, Suppression of ambipolar current in ...
  • K. Boucart and A. M. Ionescu, Length scaling of the ...
  • J. Knoch, S. Mantl, and J. Appenzeller, Impact of the ...
  • S. Garg and S. Saurabh, Improving the scalability of SOI-Based ...
  • J.-S. Jang and W.-Y. Choi, Ambipolarity factor of tunneling field-effect ...
  • T. Krishnamohan, D. Kim, S. Raghunathan, and K. Saraswat, Double-Gate ...
  • N. Dagtekin and A. M. Ionescu, Impact of super-linear onset, ...
  • International Technology Roadmap for Semiconductors 2.0 , Available on: https://www.semiconductors.org/wp-content/uploads/2018/06/0_ ...
  • S. Saurabh and M. J. Kumar, Impact of strain on ...
  • D. B. Abdi and M. J. Kumar, In-built N+ pocket ...
  • M. Karbalaei and D. Dideban, A novel silicon on insulator ...
  • D. S. Atlas, Atlas user’s manual. Silvaco International Software, Santa ...
  • C. Anghel, A. Gupta, A. Amara, and A. Vladimirescu, 30-nm ...
  • Y. Taur and T. H. Ning, Fundamentals of modern VLSI ...
  • J.-P. Colinge, Silicon-on-Insulator Technology: Materials to VLSI: Materials to VLSI, ...
  • H. L. Skriver and N. Rosengaard, Surface energy and work ...
  • B. Dorostkar and S. Marjani, DC analysis of pnpn tunneling ...
  • H. Nam, M. H. Cho, and C. Shin, Symmetric tunnel ...
  • K. M. Choi and W. Y. Choi, Work-function variation effects ...
  • نمایش کامل مراجع