Approaches for Efficient Hardware Realization of the Advanced Encryption Standard Algorithm on the Railway Industry Application

In this paper we provide an overview on different approaches for efficient hardware realization of the Advanced Encryption Standard algorithm, Rijndael. Various methods to enhance speed and reduce the critical path and area of each round unit are addressed. Resource sharing issues between encryptor and decryptor which are important when both encryptor and decryptor need to be implemented in a sma ll area are discussed. The ways to reduce power consumption and countermeasure side channel attacks are also explained. This encryption method is very suitable for increasing the reliability of information in the communication of railway. Also it implemented on the information which is coded in magnetic stripe card in the Automatic Fare Collection System.

کلیدواژه ها:

Advanced Encryption Standard Algorithm ، Rijndael ، FPGA