A New Architecture for Efficient Implementation of Neuromorphic Networks based on Nanodevice

سال انتشار: 1390
نوع سند: مقاله کنفرانسی
زبان: انگلیسی
مشاهده: 1,818

فایل این مقاله در 8 صفحه با فرمت PDF قابل دریافت می باشد

استخراج به نرم افزارهای پژوهشی:

لینک ثابت به این مقاله:

شناسه ملی سند علمی:

SASTECH05_223

تاریخ نمایه سازی: 22 مرداد 1391

چکیده مقاله:

This paper presents a new architecture for efficient implementation of neural network in hybrid CMOS/Nano hardware system. In this new architecture, latching switches are used in order to determine synaptic weights and each synaptic weight is implemented by just one latching switch. Using this new architecture, not only the CrossNet can be trained dynamically but also the number of CMOS transistors is decreased significantly. The results show that the proposed architecture leads to the higher speed, lower power consumption, and higher tolerance in the network compared to similar networks using other architectures. Therefore, the proposed structure has a huge potential to become an efficient implementation of neuromorphic networks based on nanodevice. In addition, the best results were achieved by implementing the proposed architecture in MLP networks

نویسندگان

مراجع و منابع این مقاله:

لیست زیر مراجع و منابع استفاده شده در این مقاله را نمایش می دهد. این مراجع به صورت کاملا ماشینی و بر اساس هوش مصنوعی استخراج شده اند و لذا ممکن است دارای اشکالاتی باشند که به مرور زمان دقت استخراج این محتوا افزایش می یابد. مراجعی که مقالات مربوط به آنها در سیویلیکا نمایه شده و پیدا شده اند، به خود مقاله لینک شده اند :
  • CrossNets as D efect-Tolerat Claassifiers" PhD Thesis, Stony Brook Univ. ...
  • Bishop, C., (1995), Neura1 Networks for Pattern Recognition. Oxford _ ...
  • Akazawa, M.and Ameniya, Y., (1997), "Boltzmann Machine Neuron Circuit Using ...
  • Ramacher, U., (1993), _ Multipro cessor and Memory Architecture of ...
  • Folling, S., Turel, O., Likharev K., (2001) _ _ ingle-electron ...
  • O.Turel and K.K. Likharev., (2003) "Crossnets: Neuromorphic Networks for Nanoelectronc ...
  • Likharev, K.K., (2008) "Hybrid CMO S/nanoel ectronic Circuit: Opportunities and ...
  • Likharev, K.K., (2003). "Nano and Giga Challenges in Microe lectronics, ...
  • D.B. Strukov, D.B., and Likharev K.K, . (2005), CMOL: Devices, ...
  • Folling, S. _ and Turel, O., and Likharev, K.K., , ...
  • Likharev, K.K., , Mayr, A. and Muckra, I. and Turel. ...
  • Turel, O. and Muckra, I. and Likharev K.K., (2003) _ ...
  • O.Turel and K.K. Likharev., (2004). "Architecture for Nanoelectronc Imp lementation ...
  • Lee, J.H., and Likhare. K.K., , (2006), _ situ training ...
  • "sAsrech 201 1, Khavaran Higher-education Institute, Mashhad, Iran. May 12-14. ...
  • See, and K. Likharev, (1999), _ _ Single-Electron Devices and ...
  • Masoumi, M., Raissi, F., Ahmadian, M. and Keshavarzi, P., (2006), ...
  • Gao, C. and Hammerstrom D., (2007) "Cortical Models On to ...
  • نمایش کامل مراجع