Speed Optimization Of A Fully Differential Full Adder Circuit

Delay and power of transistors are in designers‟ mind from the appearance of digital electronic circuits. Among digital electronic basic circuits full adder is an important element of integrated circuits. In this paper we have simulated a fully differential full adder in HSPICE and extracted the timing characteristics of this logic circuit. Then, by using HSPICE, describes an optimization in timing characteristic of carry-generator circuit by transistors sizing and finds the optimum speed and the sizes of transistors in circuit. Finally, compare the power consumption and speed of carry-generator circuit for active load and cross-coupled load. By comparing simulation results we found that the power consumption of cross-coupled load circuit is less than power consumption of active load circuit because of the effect of the differential pair and small DC power dissipation in them. When controlling the power dissipation of circuit is important, mainly in large scale logic circuits, we could use the cross-coupled style as load of our circuit and differential logics as our architecture style as a useful types of design.

کلیدواژه ها:

Speed Optimization ، Fully Differential Full Adder ، Transistor Sizing ، HSPICE ، Power Dissipation