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Extracting IP-Cores of a Digital Design for New Top-Down Binding and Reuse of HDL Modules

عنوان مقاله: Extracting IP-Cores of a Digital Design for New Top-Down Binding and Reuse of HDL Modules
شناسه ملی مقاله: ICEE15_195
منتشر شده در پانزدهیمن کنفرانس مهندسی برق ایران در سال 1386
مشخصات نویسندگان مقاله:

Sarang Kezemi Nia - Microelectronics Research Center, Urmia University , Urmia , Iran
Ghaznavi-Ghoushchi - Microelectronics Research Center, Urmia University , Urmia , Iran

خلاصه مقاله:
In hardware description languages (HDL), modular design and reuse of the previously designed components are widely used. It impacts on the time – To- Market and life – cycle of the design components. In this paper we present a method to extract software intellectual properties (IP) from a given HDL design. The extracted IP cores are in perlilog [1]templates which can be used for a new binding by perlilon . our proposed approach gives a systematic procedure in extraction, top-down bunding and reuse of HDL modules. A new framework for declaration of modules is introduced. Experimental results of applying the proposed algorithms on a set of complete HDL designs are also presented.

کلمات کلیدی:
Hardware Description Languages (HDL) Digital Design ,IP cores , Top - Down binding IP Reuse

صفحه اختصاصی مقاله و دریافت فایل کامل: https://civilica.com/doc/25264/