Samavi - Department of Electrical and Computer Engineering, Isfahan University of Technology, Isfahan, Iran
Habibi - Department of Electrical and Computer Engineering, Isfahan University of Technology, Isfahan, Iran
Roshanbin - Department of Electrical and Computer Engineering, Isfahan University of Technology, Isfahan, Iran

In this paper a new method for fast and low power fiactal coding is presented. The method introduced is based on the classification of domain and range blocks according to their subsampled binary representation. The technique although greatly reduces power consumption and increases processing speed bzrt has little efJect on the degradation of the output result compared to the available fractal techniques. In order to show the functionality of the proposed algorithm, the architecture was implemented on a FPGA chip. It was ' further shown that the power consumption is reduced by the proposed architecture. The resulted compression ratios, PSNR error, gate count, compression speed and power consumption are compared against the existing designs. Applications of the proposed design in certain fields such as mass volume database coding are also discussed

Fractal, image compression, VLSI, low power