Hassan Asgharian - Amirkabir University of Technology
Mehdi Salmani Jelodar - Tehran University
Masoud Kassaei - Iran University of Science and Technology
MohammadReza Jahed Motlagh - Iran University or science and technoligy

Deterministic test generation algorithms are highly complex and time-consunung. Test generation requires new approach to generate test vectors under several constraints such as high fault coverage, testing time, and testing power. In this paper, a parallel genetic algorithm-based test ystem is presented to handle constraints mentioned above. This system is capable of high fault coverage for digital circuits. Here, we use an incremental approach to achieve minimum sequence of test vectors to reduce testing time and power consumption. A general fault simulator is employed to calccllate fault coverage. Experimental results show high k ~ dcto verage with ferv test vectors for most of the ISCAS benchmark ircuits. Achieved results show, our system oritperforms over the other traditional automa tic test vector generation algorithms. In some cases we have an improvement in test vector size more than two times compared to other algoritluns.

Automatic test pattern generation, Parallel GA, Fault coverage