Hashem Zare Hoseini - IC Lab., Electrical & Computer Engineering Department, University of Tehran, Iran
Mohammad Farazian,
Omid Shoaei

In this paper a 144dB, forth-order single-loop Delta-Sigma modulator has been presented with an over- sampling ratio of 1024 and an overload factor of –1.24 dB for a bandwidth of 1000 Hz with a new low power integrator in the front-end of the modulator. In this integrator two large mismatch-free capacitors are well embedded to strongly attenuate the input KT/C noise without using any large sample or hold capacitors. Therefore, the first integrator can be easily designed with a little power and area consumption. Also CDS used in the front-end integrator strongly reduces the 1/f noise and cancels out op-amp’s offset. Thewhole modulator consumes only 8.5mW from a single 3.0V supply in a 0.6-μm CMOStechnology.

Analog to digital converter, delta sigma modulator, switched capacitor circuit, thermal noise