Akram Nasrabadi - Khorasan Razavi,Neyshabur, Science and Research Branch, Islamic Azad University , Department of Electrical Engineering, Neyshabur, Iran
Mohammad Javadian Sarraf - Islamic Azad University, Mashhad Branch, Department of Electrical Engineering, Mashhad, Iran

In this paper, the design and simulation of a silicon nanowire transistors, gate all around, cylindrical MOSFETs with four metals gate is presented .The MOS transistors, which are main part of LSI system, must be miniaturized to obtain better performance and bring down costs.And the gate dielectric, which separates the gate electrode from carrier passage, must also be thinner following the scaling law. Shrinking device dimensions leads to a reduction in the thickness of the gate dielectric (sio2) to less than 1nm in, which is already causing problems in the miniaturization MOSFETs, such as short channel effects and leakage current will be. In order to fix this problems, the gate dielectric with k higher and thicker, and four metal with different work functions, the gate is used .In this structure, the gate electrode consists of four materials M1, M2, M3 and M4 of different workfunctions deposited over respective lengths L1, L2, L3 and L4 on the gate oxide layers. The gate materials are chosen in such a way that ,the gate material at the source end is with the highest work function called the control gate and the material at the drain end is with the lowest work function. In this study,simulator Atlas Silvaco device Simulator is used for simulation. In this study, the transistor is Junctionless. In this paper, the effect of different ratios (Gate Length to the Radius of the Nanowires) on DIBL , Ion, Ioff, Vth and also on the characteristic Id- Vd been investigated.. By increasing ratios (Gate Length to the Radius of the Nanowires), DIBL, Ion, Ioff reduction and Vth increases .

Silicon Nanowire MOSFETs,Cylindrical GAA , Gate Length to the Radius of the Nanowires, Gate of Four Metal