Hamidreza Ghanbari Khorram - Department of Electrical Engineering, Hamedan University of Technology, Hamedan ۶۵۱۵۵, Iran
Alireza Kokabi - Department of Electrical Engineering, Hamedan University of Technology, Hamedan ۶۵۱۵۵, Iran

Several different Schmitt trigger topologies are proposed and compared for obtaining low-dissipation power characteristics. The proposed architectures are implemented based on hybrid CMOS-CNTFET technologies. These topologies are consisting of several comparator methods such as conventional 6T, shunted PMOS and self-biasedcomparators. Here, we consider these techniques for three technologies. These technologies are CMOS 32nm, DGFinFET and CNTFET 23nm. The best and lowest obtained dissipation power in the CMOS, CNTFET and FinFET are reported to be 9.57 pW, 13.4 nW and 9.6 nW, respectively which all observed for the 4T1 topology. The second lowest one is also marginally higher than these values and is reported to be 9.57 pW, 12.4 nW and 12.4 nW implemented on CMOS 32nm, CNTFET and FinFET technologies, respectively and the single-biased transistor topology is considered. All the proposed topologies demonstrate significant power dissipation mitigation with respect to that of conventional Schmitt trigger technique.

CNTFET, FinFET, Schmitt trigger, CMOS