رزومه علمی شاهین حسابی

دکتر شاهین حسابی

دانشیار گروه دانشگاه مهندسی کامپیوتر صنعتی شریف

چاپ

معرفی

استان

تهران

شهر

تهران

عضویت شاهین حسابی در مجامع و انجمنهای علمی

سمتهای علمی و اجرایی شاهین حسابی در مجلات و ژورنال‌های معتبر ایران

مجله پیشرفت در تحقیقات کامپیوتری (هیات تحریریه)

سمتهای علمی و اجرایی شاهین حسابی در کنفرانس ها و نشستهای معتبر ایران

دانشگاه صنعتی شریف (عضو هیات علمی)
بیست و هفتمین کنفرانس بین المللی کامپیوتر انجمن کامپیوتر ایران (دبیر علمی)
اولین نمایشگاه مجازی رایانکس ایران (دبیر جلسه)

مقالات بین المللی شاهین حسابی

"Low-overhead thermally resilient optical network-on-chip architecture", Elsevier BV, (2019), Vol 20, No : 31-47

"A low-power single-ended SRAM in FinFET technology", Elsevier BV, (2019), Vol 99, No : 361-368

"A thermally-resilient all-optical network-on-chip", Elsevier BV, (2019), Vol 99, No : 74-86

"A low-leakage and high-writable SRAM cell with back-gate biasing in FinFET technology", Springer Science and Business Media LLC, (2019), Vol 18, No 2: 519-526

"DuCNoC: A High-Throughput FPGA-Based NoC Simulator Using Dual-Clock Lightweight Router Micro-Architecture", Institute of Electrical and Electronics Engineers (IEEE), (2018), Vol 67, No 2: 208-221

"SPONGE", ACM, (2018), Vol , No :

"Behavioral-level hardware trust: Analysis and enhancement", Elsevier BV, (2018), Vol 58, No : 24-33

"A robust and low-power near-threshold SRAM in 10-nm FinFET technology", Springer Science and Business Media LLC, (2018), Vol 94, No 3: 497-506

"Topology exploration of a thermally resilient wavelength-based ONoC", Elsevier BV, (2017), Vol 100, No : 140-156

"A bio-inspired method for hardware Trojan detection", IEEE, (2017), Vol , No :

"Heterogeneous redundancy to address performance and cost in multi-core SIMT", ACM, (2017), Vol , No :

"SMART", ACM, (2017), Vol , No :

"Thermal and power aware task mapping on 3D Network on Chip", Elsevier BV, (2016), Vol 51, No : 157-167

"TooT: an efficient and scalable power-gating method for NoC routers", IEEE, (2016), Vol , No :

"AdapNoC: A fast and flexible FPGA-based NoC simulator", IEEE, (2016), Vol , No :

"Impact of on-chip power distribution on Temperature-Induced Faults in Optical NoCs", IEEE, (2016), Vol , No :

"A Fault Tolerant Parallelism Approach for Implementing High-Throughput Pipelined Advanced Encryption Standard", World Scientific Pub Co Pte Lt, (2016), Vol 25, No 09: 1650113

"Application-based dynamic reconfiguration in optical network-on-chip", Elsevier BV, (2015), Vol 45, No : 417-429

"Cluster‐based approach for improving graphics processing unit performance by inter streaming multiprocessors locality", Institution of Engineering and Technology (IET), (2015), Vol 9, No 5: 275-282

"Low Energy yet Reliable Data Communication Scheme for Network-on-Chip", Institute of Electrical and Electronics Engineers (IEEE), (2015), Vol 34, No 12: 1892-1904

"Heuristic algorithm for periodic clock optimisation in scheduling‐based latency‐insensitive design", Institution of Engineering and Technology (IET), (2015), Vol 9, No 3: 165-174

"An Efficient Synchronization Circuit in Multi-Rate SDH Networks", Springer Science and Business Media LLC, (2014), Vol 39, No 4: 3101-3109

"QuT: A low-power optical Network-on-Chip", IEEE, (2014), Vol , No :

"Power-efficient prefetching on GPGPUs", Springer Science and Business Media LLC, (2014), Vol 71, No 8: 2808-2829

"Temperature control in three‐network on chips using task migration", Institution of Engineering and Technology (IET), (2013), Vol 7, No 6: 274-281

"Fully contention-free optical NoC based on wavelenght routing", IEEE, (2012), Vol , No :

"ONC3: All-Optical NoC Based on Cube-Connected Cycles with Quasi-DOR Algorithm", IEEE, (2012), Vol , No :

"Throughput enhancement for repetitive internal cores in latency-insensitive systems", Institution of Engineering and Technology (IET), (2012), Vol 6, No 5: 342-352

"Power-efficient deterministic and adaptive routing in torus networks-on-chip", Elsevier BV, (2012), Vol 36, No 7: 571-585

"Scalable architecture for a contention-free optical network on-chip", Elsevier BV, (2012), Vol 72, No 11: 1493-1506

"GPH: A group-based partitioning scheme for reducing total power consumption of parallel buses", Elsevier BV, (2011), Vol 35, No 1: 68-80

"Hierarchical opto-electrical on-chip network for future multiprocessor architectures", Elsevier BV, (2011), Vol 57, No 1: 4-23

"An Optical Wavelength Switching Architecture for a High-Performance Low-Power Photonic NoC", IEEE, (2011), Vol , No :

"All-optical wavelength-routed noc based on a novel hierarchical topology", ACM Press, (2011), Vol , No :

"Power efficient nanophotonic on-chip network for future large scale multiprocessor architectures", IEEE, (2011), Vol , No :

"A Low Cost circuit level fault detection technique to Full Adder design", IEEE, (2011), Vol , No :

"Efficient periodic clock calculus in latency-insensitive design", IEEE, (2011), Vol , No :

"Hierarchical on-Chip Routing of Optical Packets in Large Scale MPSoCs", IEEE, (2010), Vol , No :

"Scalable Architecture for Wavelength-Switched Optical NoC with Multicasting Capability", IEEE, (2010), Vol , No :

"Low Power Encoding in NoCs Based on Coupling Transition Avoidance", IEEE, (2009), Vol , No :

"Contention-free on-chip routing of optical packets", IEEE, (2009), Vol , No :

"The ODYSSEY approach to early simulation-based equivalence checking at ESL level using automatically generated executable transaction-level model", Elsevier BV, (2008), Vol 32, No 7: 364-374

"A FRAMEWORK FOR OBJECT-ORIENTED EMBEDDED SYSTEM DEVELOPMENT BASED ON OO-ASIPS", World Scientific Pub Co Pte Lt, (2008), Vol 17, No 06: 973-993

"Caspian: A Tunable Performance Model for Multi-core Systems", Springer Berlin Heidelberg, (2008), Vol , No : 100-109

"System-Level Assertion-Based Performance Verification for Embedded Systems", Springer Berlin Heidelberg, (2008), Vol , No : 243-250

"Timing verification of distributed network systems at higher levels of abstraction", IEEE, (2008), Vol , No :

"A Novel Partitioned Encoding Scheme for Reducing Total Power Consumption of Parallel Bus", Springer Berlin Heidelberg, (2008), Vol , No : 90-97

"Integration of System-Level IP Cores in Object-Oriented Design Methodologies", Springer Berlin Heidelberg, (2008), Vol , No : 106-114

"Polymorphism-Aware Common Bus in an Object-Oriented ASIP", Springer Berlin Heidelberg, (2008), Vol , No : 115-122

"Using on-chip networks to implement polymorphism in the co-design of object-oriented embedded systems", Elsevier BV, (2007), Vol 73, No 8: 1221-1231

"DotGrid: a .NET-based cross-platform software for desktop grids", Inderscience Publishers, (2007), Vol 3, No 3: 313

"An On-Line BIST Technique for Stuck-Open Fault Detection in CMOS Circuits", IEEE, (2007), Vol , No :

"A performance and functional assertion-based verification methodology at transaction-level", IEEE, (2007), Vol , No :

"Empirical Analysis of the Dependence of Test Power, Delay, Energy and Fault Coverage on the Architecture of LFSR-Based TPGs", IEEE, (2007), Vol , No :

"GABIST: A New Methodology to Find near Optimal LFSR for BIST Structure", IEEE, (2007), Vol , No :

"An Empirical Investigation of Mesh and Torus NoC Topologies Under Different Routing Algorithms and Traffic Models", IEEE, (2007), Vol , No :

"Analysis and Fast Estimation of Energy consumption in template based QDI Asynchronous Circuits", IEEE, (2007), Vol , No :

"Evaluation of Traffic Pattern Effect on Power Consumption in Mesh and Torus Network-on-Chips", IEEE, (2007), Vol , No :

"An assertion-based verification methodology for system-level design", Elsevier BV, (2007), Vol 33, No 4: 269-284

"Implementation of a jpeg object-oriented ASIP", ACM Press, (2007), Vol , No :

"Assertion-based debug infrastructure for SoC designs", IEEE, (2007), Vol , No :

"DotGrid: A .NET-based cross-platform Grid computing infrastructure", IEEE, (2006), Vol , No :

"A data prefetching mechanism for object-oriented embedded systems using run-time profiling", IEEE, (2006), Vol , No :

"On the Hardware-Software Partitioning: The Classic General Model (CGM)", IEEE, (2006), Vol , No :

"A Reconfigurable Cache Architecture for Object-Oriented Embedded Systems", IEEE, (2006), Vol , No :

"A Table-Based Application-Specific Prefetch Engine for Object-Oriented Embedded Systems", IEEE, (2006), Vol , No :

"DESIGN OF VARIABLE FRACTIONAL DELAY FIR FILTERS WITH CSD COEFFICIENTS USING GENETIC ALGORITHM", World Scientific Pub Co Pte Lt, (2005), Vol 14, No 06: 1145-1155

"A Fault Tolerant Approach to Object Oriented Design and Synthesis of Embedded Systems", Springer Berlin Heidelberg, (2005), Vol , No : 143-153

"Rapid design space exploration of DSP applications using programmable SoC devices-a case study", IEEE, (null), Vol , No :

"Design of variable fractional delay FIR filters using genetic algorithm", IEEE, (null), Vol , No :

"High-level symbolic simulation using integer equations", IEEE, (null), Vol , No :

"Overhead-free polymorphism in network-on-chip implementation of object-oriented models", IEEE Comput. Soc, (null), Vol , No :

"Software Implementation of MPEG2 Decoder on an ASIP JPEG Processor", IEEE, (null), Vol , No :

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یک متدولوژی مجتمعسازی هستههای IP در یک محیط طراحی شیءگرای سیستمهای نهفته

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A Combined Method to Improve Sequential Circuit Test Generation

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بهبود عملکرد الگوریتم پنهانسازی خطای G.729 برای کاربرد VoIP

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سال 1384